A technique has been developed in recent years for reducing the size of a semiconductor device by arranging a plurality of solder balls in advance on the surface of a wiring board, placing the semiconductor chip over the solder balls, and connecting the semiconductor chip to the wiring board by melting the solder balls. Examples of this type of semiconductor device include a FCBGA (Flip Chip Ball Grid Array) and a WLCSP (Wafer Level Chip Size Package). Wiring boards also include multilayer wiring boards in which a plurality of resin layers having wiring embedded therein are layered, e.g., an MLTS (Multi Layer Thin Substrate) (trade name) structure and other package substrates.
However, this technique has such problems as the following. Specifically, the silicon material of the semiconductor chip and the resin of the wiring board have different thermal expansion coefficients. Therefore, even when care is taken so as to place the semiconductor chip on the wiring board without applying force to the solder balls during mounting, the semiconductor chip and the wiring board still contract differently from each other when the semiconductor device is cooled to room temperature, causing warping in the semiconductor device, and exerting force on the solder balls. When the semiconductor device is subjected to repeated cycles of heating and cooling from changes in the outside temperature and heat that accompanies the operation of the semiconductor chip, fatigue fracture can occur in the solder balls, and electrical connections can be broken.
Attempts have been made in the past to form a wiring board from as hard a resin as possible in order to prevent this problem and enhance the reliability of connections in the semiconductor device. This was to minimize warping of the semiconductor device and the deformation of the wiring board by increasing the rigidity of the wiring board. For example, a technique is disclosed in Patent Reference 1 in which an insulating material having an elastic modulus of 10 GPa or higher is used as the material for forming the wiring board.    [Patent Reference 1] Japanese Laid-Open Patent Application No. 2002-198462